Studying The Knowledge Of Ecad Systems Information Technology Essay

Studying The Knowledge Of Ecad Systems Information Technology Essay

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Throughout the learners time at college, ECAD packages have been used on a regular basis. This assignment aims to provide evidence of the learner's abilities and knowledge in these ECAD systems. Procedures, designs and simulation evidence will be included to cover the criterion.

A series of examples will be documented in this report, the first being of an analogue circuit design of a sallen and key filter; this was completed as part of the operational amplifier unit at HND level.

For this first analogue circuit to take a logical approach to the understandings of the project process a project management template was used. The template split the project process into the following categories:-

The circuit that was designed and analysed is a sallen and key filter. In particular a 1st order low pass sallen and key filter with a cut off frequency of 1 KHz and a Q factor of 0.5.

The basic sallen and key filter configuration is generally a 2nd order system, meaning it has two stages before the amplifier, and the output after the 3dB point decays at a rate of 40dB per decade. Also to note the above is a unity gain amplifier meaning no feedback is present thus a gain of 1 is present.

Although the basic Sallen Key filter is second order, first order circuits are available. In this way any number of Sallen and Key filters can be cascaded to give any order of filter required with any Q factor.

The filter that is required to be built is still part of the sallen and key topology but is only a 1st order system; this means one stage before the amplifier and a decay rate of 20 dB per decade.

Often it is required to introduce gain in the circuit in order to reach desired Q factors. Although for the circuit that is to be designed, as only one stage is required therefore it will have a Q factor of a ½ or 0.5 and thus no need for changing the circuit from unity gain as this is the Q factor specified.

Circuit Design

The Specifications of the circuit were as follows:-

1st Order

Low Pass

Q of 0.5

Cut off frequency of 1kHz

As mentioned earlier the circuit design for a 1st order filter with a Q factor of 0.5 only requires 1 single stage, and unity gain is sufficient to achieve the Q factor of 0.5.

From the cut off frequency it is possible to work out the capacitor component values required, firstly a resistor value needs to be chosen this can be anything but it is advised to keep it high as to not affect connected devices. For this example I have chosen 5kΩ.

If the cut off frequency Fc= 1/2Ï€RC=1 KHz

Then

C=1/2Ï€*5000*1000=0.0000000318 or 31.8nF

With the component values chosen the circuit was drawn on Multi-sim this is part of the evidence of the learners ability with ECAD packages.

Now that the circuit has been designed, then it can be tested using multi-sim this shows ECAD simulation skills of the learner.

Shown below is the circuit running with a bode plotter connected, this gives a graphical frequency response from the circuit the expected results are that the 3dB point should occur at 1000 Hz or 1 kHz this is what the circuit has been designed to do.

As you can see from the screen shot above the circuit simulation was a success, the -3dB point occurred at around 1 KHz and the response that can be seen from the bode plot is that of a critically damped system. Also worth noting is that the plot shows the filter is a low pass filter as it starts with a high gain at low frequencies and the goes lower as the frequency gets passed 1 KHz and higher.

The bode plot can be seen in more detail in the expanded view below:-

The cursors on the above bode plot have been used to show the -3dB point which is at 1 kHz, on the next plot the cursors have been used to show the decay rate, of which is expected to be 20 dB per decade as this is a first order system.

Each vertical line represents one decade on the above graphical plot, a cursor has been placed on two lines in order to measure the decay on the gain, as you can see the decay is -20.0496 dB per decade which is what is expected of a first order system.

Further Analysis of the Sallen and Key Filter

In order to investigate these devices fully, a couple of changes to the circuit design are required.

So firstly to show the effect of changing the value of the components, the capacitor value will be halved this should have the effect of increasing the cut off frequency this can be seen in the screen shot below:-

The screen shot shows the learner modifying the circuit and re-testing the circuit, the cut off frequency is now 2 kHz double from before.

Now back to the original circuit with a cut off frequency of 1 kHz, the capacitor and resistor are now going to change positions. From the research done before it has been found that this will have the effect of turning this filter into on with a different application. From a low pass filter this will turn into a high pass filter if the resistor and capacitor or interchanged.

The new circuit is shown below with the new simulation results on the bode plot:-

The new configuration still has a cut off point of 1 kHz but now has the function of filtering signals with frequencies below 1 kHz and lets the signals above this through hence this is now a high pass filter.

Again an expanded bode plot is included showing the 3dB point, the whole sallen and key project is evidence of the learners ECAD skills.

To evaluate the circuit has been designed and shown working on ECAD this therefore has proved the design stage and created a method for the simulation/test stage. So to conclude the circuit operated as it was expected to, for example the initial design was specified to have a cut off frequency of 1 kHz, when simulated on ECAD the circuit operated with a cut off point of around 1 kHz. All the tests and results have been described earlier. Thus now a test procedure could be created to document what has been found through ECAD but to prove the skills gained this will be transferred into a real life activity and thus proving the learners ability.

If this project was to be done in a real life situation then a test procedure would be part of the project, but before the circuit is built practically the circuit is tested on an ECAD package as to rule out any problems and build a test procedure before the more time costly practical starts thus saving time and money.

So obviously to complete the test procedure the same circuit as already described was built practically at college.

The test procedure can be found in appendix B, the one that was test piloted by the learner is included as well as a blank procedure.

The test procedure was carried out, and with reference to the completed test procedure the circuit passed all the instructions and tests set out in the procedure. So to summarise the practically built circuit passed the test procedure that was designed from ECAD design and simulations.

The results from the test procedure are as follows:-

Frequency Hz

Input V

Output V

Gain

Gain dB

3dB Point

0

3.05

3.05

1

0

-3

100

3.05

3.05

1

0

-3

200

3.05

3.05

1

0

-3

400

3.05

3.05

1

0

-3

600

3.1

2.45

0.790323

-2.04391

-3

800

3.1

2.3

0.741935

-2.59268

-3

1000

3.1

1.85

0.596774

-4.4838

-3

2000

3.1

1.14

0.367742

-8.68914

-3

10000

3.1

0.24

0.077419

-22.223

-3

100000

3.1

0.04

0.012903

-37.786

-3

 

 

 

 

 

 

The table above shows the results gained from the practical circuit using the test procedure.

In order to illustrate the above results and thus make the verdict that the circuit has performed to expectations the results were put in a graphical bode plot form. The bode plot can be found on the following page.

The graph above shows the gain of the filter vs. the frequency, a line has been added to the plot to identify where the -3dB point occurs. If the plot is analysed the -3dB point of the filters output can be found to occur at around 750 Hz. This cut off frequency is sufficiently close to the one expected of 723Hz.

In reference to the test procedure, these results have proved that the ECAD work has made a test procedure that correctly assesses a practically built circuit of the same configuration.

While the report is on the subject of analogue circuits, to include some more evidence of the learners ECAD abilities another design and test example is included next.

The next piece of evidence of the learners use and skill of ECAD systems is a two port network symmetrical T circuit; this was used as part of an assignment in HND further principles.

The circuit below was built on Vero board and was tested using an impedance analyser set at 1000Hz the characteristic impedance was measured. The theoretical characteristic impedance of the circuit will be calculated so that a comparison between the theory and practical results can be done to see any differences if any, then any comments required upon the errors will be included. Finally a computer simulation will be done to further examine the theory and practical results and to back up any assumptions.

The components above were the closest possible values that were in stock to the ones requested.

The components selected were also checked for there real values, as such components come with a tolerance; the actual value can be of difference enough to affect calculations.

It is important that these components were measured before they were soldered into circuit as this could give errors when trying to determine a particular components value.

Practical Component Values

Resistor

Stated Value

Measured Value

R1

330Ω

324Ω

R2

430Ω

425Ω

The circuit was built on Vero board and components soldered in place; which is important to note at this point can have an affect on results as joints can add resistance to the circuit along with other resistance such as copper track resistance.

An impedance analyser was run at 1000Hz to obtain the internal impedance of the network in two conditions, when its second port was open circuit and also when it was short circuit.

The results of the practical are to follow.

To determine the characteristic impedance theoretically the component values were inserted in the formula found earlier in the report:-

But in this case resistor values so:-

Therefore

The results I obtained from the impedance analyser

Test

Frequency

Impedance

Open Circuit

1000Hz

754.3871Ω

Short Circuit

1000Hz

513.3995Ω

From the above results I can determine the characteristic impedance from the formulae derived earlier in the report:-

Therefore

As mentioned earlier also simulating this circuit on computer simulation software gives a further level of evidence to prove the formulae and practical results.

The computer simulation software has the standard resistor values that were used but an important thing to note is that there is not any variance in the value of the components, thus if a 330Ω resistor is chosen then its resistance will be 330Ω, and as for that the computer simulation should be as near as the same as the theory as possible.

As this is such a reliable test then it is a good way of proving the theoretical as any errors will be highlighted by the computer simulation test.

Below shows the circuit drawn on Multi-sim and connected in circuit is a network analyser that does the same tests as the impedance analyser used practically. This is the evidence of the learner's skill with ECAD systems.

To follow is a screen shot of the T network short circuit test simulation using a network analyser:-

Results Obtained From Multi-sim

Test

Frequency

Impedance

Open Circuit

1000Hz

760Ω

Short Circuit

1000Hz

516.7105Ω

Characteristic Impedance Determined from same method as before:-

Therefore

When this is compared to the theoretical value for Zo, it can be seen that as expected the computer simulation gave perfect results.

Theory vs. Practical vs. Computer Simulation

Characteristic Impedance

Theory

626.660°Ω

Practical

622.340°Ω

Computer Simulation

626.660°Ω

Important to note at this stage as working with a purely resistive network the frequency would not affect the circuit impedance, and no phase angle difference is produced by the circuit either.

Comparing practical results to theory the difference can be expressed as a per unit error this represents the errors produced in the practical due to mainly the resistors not being exactly the resistance that they are rated at this cannot be avoided. Use of lower tolerance resistance my get the errors down to a minimum but errors will still exist.

Theory- practical error,

From the above it is apparent that the errors that have occurred between practical and theoretical are very small and a combination of lower than stated resistance values and stray resistance caused by solder joints, and copper track have made the errors very small.

From the table you can see that as expected the computer simulation results are exactly the same as the theoretical and therefore have the same error in common with the practical results, thus this confirms the results obtained throughout the practical.

More additional evidence will be included later in the report but now the second project is to be described this time it will be of a digital logic circuit.

Again in order to take a logical approach to the understandings of the project process a project management template was used. The template split the project process into the following categories:-

Persons involved and their roles

Main objects, notably, research, design, build and evaluate

Time planning

Risks (no risks existed)

Constant Milestone recording and evaluation

A final project tick sheet, to assess the management is complete

The project template that was filled out for this analogue circuit is in appendix C of this report.

The circuit that was designed and analysed is an 8bit gray code to binary code converter.

In the following part of the report the design process will be explained and then the schematic design and simulation on multi-sim will be documented.

8bit Gray to binary code converter:

As there is a conversion process from gray to binary, firstly the process was found in a book and was tried a few times on a few conversions then a small truth table was completed of gray to binary.

The first part of the conversion process that is an important factor is that the most significant digit is always used and not changed, so in the circuit this mean the last input/most significant digit is an output.

Then we work the way from the most significant to the least significant digit, by taking the output of the digit before and if it and the next input digit are a two 1s or two 0s then the next output is to be a 0, but if they are a 1, 0 or 0, 1 then the next output digit is to be a 1. This process is followed till the least significant digit is reached.

Shown below is an 8bit Gray to Binary conversion that is decimal number 5.

0 0 0 0 1 1 1

0 0 0 0 0 1 0 1

If you start at the left hand side then proceed right then the output in binary code is 00000101 which converts to decimal as 4 + 1 = 5. Exactly the same decimal number which was inputted in gray code

So having accomplished converting sum gray code into binary then now all was left was to find a gate that if its input were 00 or 11 gave an output of 0 and if its input were either 10 or 01 gave an output of 1. From looking at a logic book it was found that the logic gate that met these characteristics was an exclusive OR gate.

All that was left now was to sketch out the circuit having found everything that is required of it and what devices are needed to implement it.

After drawing the circuit it was simulated on the computer on a program called multi-sim to check that it performed in the way that I expected, a screen shot of the simulation is below.

Once I had finished the computer simulation I decided to build a real circuit on a logic circuit simulation board, but I simply created part of the circuit jus for experimental purposes.

The idea of the simulation was that a gray code number would be subject on the input and the output would be the corresponding binary number of the input stage. So thus the expected results were that the correct binary number was outputted from the circuit.

Below are the input and the expected output:-

Decimal

Binary

Gray

10

00001010

00001111

So the decimal number 10 (00001111 for gray) was the input and as you can see from the screen shot below the circuit has performed as expected and produced the binary 00001010 which can be converted to be a decimal number of 10. This is evidence of the learner's digital logic skill when using ECAD systems.

To now evaluate this has given evidence of the project that was completed by using a project management template. Involved in this project was the design, schematic circuit design and simulation of an 8 Bit gray code converter.

From the knowledge that was gained through doing the activities described a fully functional test procedure can be made. This procedure should be so that anyone could use a computer to test this circuit and evaluate its performance, in this particular procedure the number 15 will be converted from gray to binary.

The test procedure can be found in the appendix D with screen shots of the tests done.

To conclude on the test procedure, all the instructions were followed and the circuit was tested as to what the method on the procedure described. As a result a correct conversion of the gray code of decimal 15 was completed. As a result this has shown the ability to not only use ECAD systems but also write a method for anyone to use them too.

Additional ECAD Evidence

In order to give more of an insight into the learner's use of ECAD based systems a few more examples will be included to show that the learner has gained experience of ECAD.

Another digital circuit is to be included, and then some work that was done comparing 3 different ECAD programs will be used to show the flexibility and adaptability of the learner, being able to apply their knowledge with different ECAD programs and to compare the results.

The next digital circuit to be described as part of confirmation of the ECAD ability is an 8 Bit Parallel to Serial Converter; this device was designed from research, then built on ECAD and tested through simulations.

Parallel to Serial Converter

The next stage of this report takes on the task of designing a parallel to serial converter in particular an 8 bit configuration. Firstly an explanation into the two data transmissions and then I will be commenting on the design process.

Parallel Communication

This involves using a cable system with each data bit of a data word being sent simultaneously along parallel data lines. Parallel communication is the faster method of communication than serial but is restricted to a maximum transmission rate of 1 M bytes per second up to a maximum transmission distance of 15m, intended for high speed short distance communication in situations where there is little electrical interference.

Serial Communication

This involves data being sent in a chain like manner along a single path way, serial communication can be used over much longer distances. Although the transmission rate is lower than parallel.

Parallel To serial conversion

This process involves taking a set of individual parallel input and putting them in a sequence down a single serial output. The process is normally accomplished by the use of a counter to provide a binary sequence for the data select inputs of a data selector.

It is possible with a particular type of flip that has both synchronous and asynchronous inputs to form a data register as mentioned earlier in the D type flip flops. The data register can be arranged to accomplish a form of data manipulation called parallel to serial conversion.

Basically the process that is required of the flip flops is to capture the input from the parallel data lines then after each clock pulse shift the data to the output serial line at the end of the shift register.

So as the way of transmitting the data could be done using D type flip flops in a shift register configuration all that was needed is a way of capturing the parallel inputs. To do this each input was put into a two input AND gate and in with the input is a load line that is switched on when the registers are wanted to capture the input, then the clock will start the transmitting process.

As the basic idea is complete the next stage was to create the circuit on multi-sim, and the final circuit design is below:-

The switches across the top represent the parallel inputs these can give either a 1 or 0 depending on the switch position, the switch on the left at the top is the load line switch this is used to set the shift register to capture the inputs, a reset switch has been included for when a new set of inputs is required and to work as a clock a switch has been used to give the user chance to check the output after each pulse.

As the circuit has been drawn the next thing would be to try the circuit by simulation on ECAD to see if it operates as it should do. The circuit should convert any combination of parallel inputs to a serial out put a screen shot of this process is to follow on the next page.

The above screenshot has been included to show the circuit in a working manner, it can be now evaluated that the circuit did work as it was expected to.

The simulation was witnessed by Terry Hopewell as part of the requirements in that particular subject of the HNC electrical course the learner was attending.

To conclude on the 8 Bit parallel to serial converter, the circuit was designed through research, and drawn on multi-sim then simulated to test the operation. All this demonstrates skill in ECAD systems.

The penultimate part of this report is an analysis that was completed as part of the ECAD unit at HND level; the analysis that took place was of three different ECAD programs. One program that has been used before and proved to give good results from theory and practical sources, and two others that have never been used before.

ECAD Package Analysis and Test

A series of test circuits will be built on each package, and measurements taken. Then a comparison of the results will be done and also the usability of the each software will be described.

The test circuits are not the most complicated circuits, as it was hard enough learning to use some of these new ECAD systems without trying to make things worse with a complicated circuit too.

Test 1 Voltage Divider

A simple voltage divider circuit, with an AC source signal.

R1 = 2 k Ω

R2 = 2 k Ω

V1 = 12V 1000 Hz AC

Expected results:-

Voltage drop across R1 and R2 is expected to be 6 Volts

Current being drawn = 12/4000= 3mA

Test 1 Multi-sim

Test 1 Multi-sim Results

V1

VR1

VR2

I1

12V

6V

6V

3mA

Test 1 OrCAD

Test 1 OrCAD Results

V1

VR1

VR2

I1

12V

6V

6V

0

Test 1 CircuitLogix

Test 1 CircuitLogix Results

V1

VR1

VR2

I1

12V

4.237V

4.237V

2.119mA

Test 1 Conclusion

Shown below is a summary of the results:-

V1

VR1

VR2

I1

Expected

12V

6V

6V

3mA

Multi-sim

12V

6V

6V

3mA

OrCAD

12V

6V

6V

0

CircuitLogix

12V

4.237V

4.237V

2.119mA

As you can see from the above, there were a few differences in results between the expected results and the results gained from the ECAD packages.

Multi-sim

This out of the three was more user friendly and got the best results, this could be down to the fact that the learner had used this package before.

OrCAD

Out of all the packages this one was found to be the hardest to use, just starting a new design takes a lot more time. The results were not bad, except the current reading, but this is probably down to user error.

CircuitLogix

Nice user interface, easy to setup the circuit and testing is just as easy as with multi-sim. The measurements taken are not so good though, this was partly due to user error and also limited options within the program. The voltage source only has an option for setting its output in peak voltage, where as in the other two packages you could set the output in RMS. As the voltmeter only measures in RMS then you get an incorrect reading. This can easily be sorted by dividing 12V by 0.7071 and gaining the corrected peak voltage to set the source at 17V. The test was repeated and the results below were gained. This should not have to be done, an option for setting the output of the source in RMS volts should be provided.

Test 1 CircuitLogix Revised

V1

VR1

VR2

I1

12V

6.003V

6.003V

3.001mA

Test 2 RC Phase Shift Oscillator Network

A three stage RC network will be used to test the ECAD systems

R1, R2, R3 = 2.2 kΩ

C1, C2, C3 = 100nF

V1 = 1V 1.778 Hz (Resonant Frequency) AC

Expected Results

Attenuation = 1/29th of the input

Phase Shift = 180 Degrees

Test 2 Multi-sim

Test 2 Multi-sim Results

Vin

Vout

Attenuation

Phase Shift

1

33mV

1/29th

179.489 Deg

Test 2 OrCAD

Test 2 OrCAD Results

Vin

Vout

Attenuation

Phase Shift

1

1V

N/A

0 Deg

Test 2 CircuitLogix

Test 2 CircuitLogix Results

Vin

Vout

Attenuation

Phase Shift

1

29.33mV

1/33

Unknown

Test 2 Conclusion

Shown below is a summary of the results

Vin

Vout

Attenuation

Phase Shift

Expected

1

0.034mV

1/29

180 Deg

Multi-sim

1

0.033mV

1/29

179.489 Deg

OrCAD

1

1V

N/A

0 Deg

CircuitLogix

1

29.33mV

1/33

Unknown

Again from the above differences have occurred between the results of the three ECAD systems, report now covers why these differences occurred.

Multi-sim

Yet again the easiest to use, and for this particular circuit the bode plotter tool was very useful for analysing the difference in phase over the bandwidth of the oscillator. The results are a good comparison of the expected results.

OrCAD

Unfortunately OrCAD failed to give any results that are close to the expected results. The reason why this circuit seems to have not worked at all is unknown. Not having a bode plotter didn't help.

CircuitLogix

CircuitLogix compared to OrCAD was a bit more positive but still not up to the results gained from Multi-sim. CircuitLogix has a close attenuation to what was expected, but unfortunately the program had no way of measuring the phase shift introduced by the circuit.

Test 3 Inverting Op-amp Circuit

Circuit to demonstrate the gain of an op-amp

Op-amp

RF = 10 k

RIN = 1 k

AC Input = 0.5V 1000 Hz

Expected Results

With the ratio of the two resistors 10k to 1k a gain of 10 should be introduced by the operational amplifier.

Vout = 0.5 x 10 = 5 Volts

Test 3 Multi-sim

Test 3 Multi-sim Results

Vin

Vout

Gain

0.5V

5V

10

Test 3 OrCAD

Test 3 OrCAD Results

Vin

Vout

Gain

0.5V

5V

10

Test 3 CircuitLogix

Test 3 CircuitLogix Results

Vin

Vout

Gain

0.5V

5V

10

Test 3 Conclusion

Below shows the summary of the results:-

Vin

Vout

Gain

Expected

0.5V

5V

10

Multi-sim

0.5V

5V

10

OrCAD

0.5V

5V

10

CircuitLogix

0.5V

5V

10

Throughout test 3 all three of the systems have successfully simulated the circuit and given the results that were expected. Although like in all the other tests none of the others can match multi-sim on the ease of use.

Evaluation of Programs

OrCAD

Although OrCAD did complete the tests, it was the most difficult to use out of the three. This made it impossible to draw complicated circuits successfully, even the simplest circuits were found to take much longer to draw and test. Another bad point about the software is inputting the simulation settings every time according to the circuit you want to test; this in other programs is done automatically, also finding the parts required for drawing circuits was far more difficult than it needs to be.

CircuitLogix

CircuitLogix is the much cheaper software out of the three; this does show in the operation and use of the software. With this in mind the performance of the package is good. Although one thing that does limit the software and was noticed when testing the RC network, the simulation only runs for a certain amount of time and then stops. This doesn't give some circuits enough time to settle and can give false results.

Multi-sim

This was by far the superior ECAD system not just for the reliability of the results gained from it, but also for the ease of use. This may be helped because of the experience that the learner has with Multi-sim. The vast amount of tools available in multi-sim for simulation is one of the best features, and the library of components is easy and simple to use.

To conclude on the evidence provided in the last part of the report, a task was given to analyse different ECAD systems, the way in which was done was to use one program that had been used before (multi-sim) and compare the results gained from two new never used programs. As it is possible to see from the results gained neither of the two gave results that are as reliable as multi-sim and nor were they as easy to use. Regardless of this, the exercise shows advanced skills in ECAD systems as picking up a new piece of software and learning how to use it in a small time scale is not easy and would not be possible for a novice who has little experience in ECAD.

The final part of the report and the final example to be included is the design and testing of a 555 clock generator circuit, this example shows the learner using a device that has many functions, the 555 integrated chip.

Design and construct a clock generator to Operate at 1Hz

From my work into combinational logic I am including in this report how to make a clock generator using a 555 timer circuit.

The 555 timer IC was first introduced around 1971 by the Signetics Corporation as the SE555/NE555 and was called "The IC Time Machine" and was also the very first and only commercial timer IC available. It provided circuit designers and hobby tinkerers with a relatively cheap, stable, and user-friendly integrated circuit for both monostable and astable applications. Since this device was first made commercially available, a myrad of novel and unique circuits have been developed and presented in several trade, professional, and hobby publications. The past ten years some manufacturers stopped making these timers because of competition or other reasons. Yet other companies, like NTE (a subdivision of Philips) picked up where some left off.

Frequently, the 555 is used in astable mode to generate a continuous series of pulses, but you can also use the 555 to make a one-shot or monostable circuit. The 555 can source or sink 200 mA of output current, and is capable of driving wide range of output devices.

The 555 has three operating modes:

Monostable mode: in this mode, the 555 functions as a "one-shot". Applications include timers, missing pulse detection, bounce free switches, touch switches, Frequency Divider, Capacitance Measurement, Pulse Width Modulation (PWM) etc

Astable - Free Running mode: the 555 can operate as an oscillator. Uses include LED and lamp flashers, pulse generation, logic clocks, tone generation, security alarms, pulse position modulation, etc.

Bi-stable mode or Schmitt trigger: the 555 can operate as a flip-flop, if the DIS pin is not connected and no capacitor is used. Uses include bounce free latched switches, etc.

Schematic symbol

The connection of the pins is as follows:

Nr.

Name

Purpose

1

GND

Ground, low level (0V)

2

TR

A short pulse high → low on the trigger starts the timer

3

Q

During a timing interval, the output stays at +VCC

4

R

A timing interval can be interrupted by applying a reset pulse to low (0V)

5

CV

Control voltage allows access to the internal voltage divider (2/3 VCC)

6

THR

The threshold at which the interval ends (it ends if U.thr → 2/3 VCC)

7

DIS

Connected to a capacitor whose discharge time will influence the timing interval

8

V+, VCC

The positive supply voltage which must be between 3 and 15 V

Clock Generator Circuit Diagram

As you can see, the frequency, or repetition rate, of the output pulses is determined by the values of two resistors, R1 and R2 and by the timing capacitor, C.

The design formula for the frequency of the pulses is:

The period, t, of the pulses is given by:

The HIGH and LOW times of each pulse can be calculated from:

The duty cycle of the waveform, usually expressed as a percentage, is given by:

An alternative measurement of HIGH and LOW times is the mark space ratio:

Before calculating a frequency, you should know that it is usual to make R1=1 kΩ because this helps to give the output pulses a duty cycle close to 50%, that is, the HIGH and LOW times of the pulses are approximately equal.

Remember that design formulae work in fundamental units. However, it is often more convenient to work with other combinations of units:

resistance

capacitance

period

frequency

Ω

F

s

Hz

MΩ

μF

s

Hz

kΩ

μF

ms

kHz

With R combined values in MΩ and C values in μF, the frequency will be in Hz. Alternatively, with R values in kΩ and C values in μF, frequencies will be in kHz. To make a circuit that operates at 1Hz then the correct components need to be chosen.

R1 should be 1kΩ, as already explained. This leaves you with the task of selecting values for R2 and C. The best thing to do is to rearrange the design formula so that the R values are on the right hand side:

Substitute for R1 and f:

Using R values in kΩ and f values in kHz, so C values will be in μF. To progress on with the design a value for C was chosen to be 2 μF.

That is:

And:

Thus the circuit looks like this:-

The resistors used adjust the duty cycle of the output, Since C1 charges through R1+R2 and discharges only through R2, duty cycles approaching a minimum of 50% are achievable if R2>>R1 so that the charging and discharging times are approximately equal.

The duty cycle can be worked out from the time that the output is high and low to give the following formula:-

Thus for the components before:-

As I had not had chance to build the circuit practically I built the 1Hz circuit on computer simulation software to prove that it operates correctly a screen shot of the circuit components, and a oscilloscope print out is below:-

As the screen shot informs, the simulation of the circuit was a success. To evaluate the clock frequency that was produced came out at around 1 Hz as expected from the design process. The oscilloscope was used to capture the output from the circuit and display it in a form that can be useful, as the oscilloscope that was used had measuring tools it was these tools that allowed easy measurements of the period and frequency. Thus this shows the use of another measurement tool in simulation of a circuit in ECAD.

Conclusion

The aim of the assignment is to provide evidence of the learner's skill and ability with ECAD systems, therefore the primary content of this report has been examples of ECAD activities completed by the learner in order to build up a compilation of evidence.

In order to provide a good range of evidence, analogue and digital circuits were chosen when deciding the examples to include in this report. As to demonstrate the ability to provide solutions to engineering problems, two circuits will be designed, one analogue and one digital. The analogue circuit that is designed in this report is the Sallen and Key filter with a cut off frequency of 1 kHz. The digital circuit that is included is an 8 bit gray to binary code converter.

The activity of designing and simulating/testing the two circuits described above has been part of a project where project management techniques have been used to complete the process. In order to document the project management techniques, two different project management templates have been completed. ECAD systems were used to design and simulate the circuits; therefore the experience of using ECAD is shown.

As to complete and finish the projects of both these two circuit, an evaluation of the circuit simulation of ECAD is provided. In addition a test procedure was made for the circuit so anyone could make the circuit and test it and evaluate it against the results gained from initial simulations.

Finally as to demonstrate a good experience and skill in the use of ECAD, more examples of circuit design and simulations have been included. Such circuits like an RC network, clock generator, and a parallel to serial converter. Also a comparison between three ECAD systems has been provided.